1. Technical Field
The present invention relates to a substrate bonding method and an electronic component. More specifically, the invention relates to a substrate bonding method for layering a first substrate and a second substrate preferably comprising at least one device, preferably a MEMS device, provided thereon. More specifically, the invention relates to a substrate bonding method for layering a substrate having a device provided thereon, preferably an IC device, and a substrate having a device provided thereon, preferably a MEMS device. In particular, the invention concerns a substrate bonding method for performing wafer level packaging on wafer substrates layered vertically as they are after assembling.
2. Related Art
In a step of manufacturing a MEMS (Micro Electro-Mechanical System), typically, a wafer having a plurality of MEMS devices provided thereon is diced into a plurality of chips, each chip (i.e., each MEMS device) is incorporated in a package housing, and an opening of the package housing is sealed with a cover.
In such a manufacturing method, however, each MEMS device is subjected to packaging using a package housing and a cover, resulting in complication of the step of manufacturing the MEMS. In course of the manufacture of the MEMS, further, dust and dirt are attached to the MEMS device, resulting in reduction of yields. Moreover, restriction to the package housing hinders miniaturization of the MEMS device.
In order to solve these problems, attention has been given to a wafer level bonding technique for packaging a MEMS device and the like in a state of a wafer, or a technique called wafer level packaging. According to this method, wafers each having a plurality of devices provided thereon, for example, a wafer having a plurality of IC devices such as CMOS provided thereon and a wafer having a plurality of MEMS devices provided thereon are layered (superimposed) vertically and then are bonded. Thus, each MEMS device and each IC device are confined in a pair within a cell formed between the wafers. Thereafter, the bonded wafers are separated into cells by dicing or the like to obtain a MEMS having a configuration that the MEMS device and the IC device are accommodated in the package formed by the wafers.
According to this manufacturing method, since the wafers are cut with the MEMS device and the IC device being confined therebetween, dust and dirt are less prone to be attached to the MEMS device and the like. Moreover, the MEMS device having a movable part is not handled in a bare chip state, leading to enhancement of yields of MEMSs. Further, the resultant MEMS is reduced in size and the number of MEMSs to be obtained from one wafer increases, leading to reduction of manufacturing costs.
However, there remain the following problems to be solved in order to put such a wafer level bonding technique to practical use.
In a case of vertically layering a wafer having an IC device such as CMOS provided thereon and a wafer having a MEMS device provided thereon and performing wafer level bonding (i.e., packaging) on the layered wafers, it is necessary to achieve electrical insulation and electrical conduction simultaneously between the vertically layered wafers. For example, bonding surfaces of the wafers must be electrically insulated whereas electrodes of the respective devices must be electrically connected. For this reason, the wafers are bonded with an insulating film being interposed therebetween (e.g., refer to JP 2007-184546 A). Herein, the insulating film on the bonding surface requires satisfactory smoothness in order to increase bonding strength between the wafers and to ensure reliability. Moreover, the insulating film also requires satisfactory smoothness in order to ensure hermeticity and sealability between the wafers.
An SiO2 film is a typical insulating film for use in a bonding surface (e.g., refer to JP 2007-184546 A). Examples of a method for forming such an SiO2 film include a film forming method using thermal oxidation (e.g., refer to JP 2004-160607 A) and a film forming method using PVD (Physical Vapor Deposition) such as sputtering (e.g., refer to JP 2007-509578 A).
According to the thermal oxidation method for thermally oxidizing a surface of an Si wafer to form an insulating film (i.e., an SiO2 film), this formed SiO2 film has satisfactory surface smoothness and thickness evenness. However, the thermal oxidation method is a high-temperature process of applying heat at about 1000° C. to a wafer in an oxygen atmosphere in order to form a film. Consequently, the heat causes damage on a wiring pattern formed on the wafer, resulting in breaks of the wiring pattern.
According to the PVD method such as sputtering, on the other hand, an SiO2 film can be formed by a process at a low temperature of about 100° C. As a result, a wiring pattern on a wafer is prevented from being damaged thermally. According to the PVD method, however, the formed SiO2 film is unsatisfactory in surface smoothness and thickness evenness. Consequently, there is a problem that it is impossible to satisfactorily increase bonding strength between the SiO2 film and the wafer and to satisfactorily ensure reliability.
In order to attain smoothness, a bonding surface is occasionally subjected to CMP (Chemical Mechanical Polishing) in manufacture of LSI and the like. However, a MEMS device has such a complicated structure that structural components, electrodes and the like are formed on both sides of a wafer. For this reason, there is a possibility that the polishing causes damage on the MEMS device. Consequently, it is impossible to attain the smoothness by the polishing, that is, it is impossible to smooth the SiO2 film formed by the PVD method, by the polishing.